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Low-, medium- and high-density reset and clock control (RCC)
RM0008
6
6.1
6.1.1
Low-, medium- and high-density reset and clock
control (RCC)
Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
High-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 256 and 512 Kbytes.
Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
This Section applies to low-, medium- and high-density STM32F10xxx devices. Connectivity
line devices are discussed in a separate section (refer to Connectivity line devices: reset
and clock control (RCC) on page 104 ).
Reset
There are three types of reset, defined as system Reset, power Reset and backup domain
Reset.
System reset
A system reset sets all registers to their reset values except the reset flags in the clock
controller CSR register and the registers in the Backup domain (see Figure 4 ).
A system reset is generated when one of the following events occurs:
1.
2.
3.
4.
5.
A low level on the NRST pin (external reset)
Window watchdog end of count condition (WWDG reset)
Independent watchdog end of count condition (IWDG reset)
A software reset (SW reset) (see Section : Software reset )
Low-power management reset (see Section : Low-power management reset )
The reset source can be identified by checking the reset flags in the Control/Status register,
RCC_CSR (see Section 6.3.10: Control/status register (RCC_CSR) ).
Software reset
The SYSRESETREQ bit in Cortex?-M3 Application Interrupt and Reset Control Register
must be set to force a software reset on the device. Refer to the Cortex?-M3 technical
reference manual for more details.
Low-power management reset
There are two ways to generate a low-power management reset:
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Doc ID 13902 Rev 9
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